Logical effort: designing fast CMOS circuits
Material type: BookPublication details: San Francisco: Morgan Kaufmann Publishers, 1999.Description: xv, 239p.: ill; 24 cmISBN:- 9781558605572
- 621.38152 SUT
Item type | Current library | Collection | Call number | Status | Date due | Barcode |
---|---|---|---|---|---|---|
Books | IIT Gandhinagar | General | 621.38152 SUT (Browse shelf(Opens below)) | Available | 016896 | |
Books | IIT Gandhinagar | General | 621.38152 SUT (Browse shelf(Opens below)) | Available | 016897 | |
Books | IIT Gandhinagar | 621.38152 SUT (Browse shelf(Opens below)) | Available | 008138 |
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686.224 EVA Practical 3D printers: the science and art of 3D printing | 620.0011 BAL Applied optimization: formulation and algorithms for engineering systems | 621.382 GAL Principles of digital communication | 621.38152 SUT Logical effort: designing fast CMOS circuits | 621.38152 SUT Logical effort: designing fast CMOS circuits | 617.89 VAL Strategies for selecting and verifying hearing aid fittings | 516.36 CAR Differential geometry of curves and surfaces |
Includes bibliographical references and index
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