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Logical effort: designing fast CMOS circuits

Sutherland, Ivan,

Logical effort: designing fast CMOS circuits - San Francisco: Morgan Kaufmann Publishers, 1999. - xv, 239p.: ill; 24 cm.

Includes bibliographical references and index

ISBN: 9781558605572

Subjects--Topical Terms:
Applied physics
Logic design
Metal oxide semiconductors
Design and construction

Dewey Class. No.: 621.38152 SUT

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