Vertical 3D memory technologies
Publication details: John Wiley & Sons Ltd. 2014 Chichester:Description: xiii; 351p. hb; 25 cmISBN:- 9781118760512
- 621.39732 PRI
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IIT Gandhinagar | 621.39732 PRI (Browse shelf(Opens below)) | 1 | Available | 028157 |
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621.39732 DEL Intelligent integrated systems: devices, technologies, and architectures | 621.39732 KUR Nanoscale semiconductor memories: technology and applications | 621.39732 MAG Advances in non-volatile memory and storage technology | 621.39732 PRI Vertical 3D memory technologies | 621.39732 RAZ Design of analog CMOS integrated circuits | 621.39732 RAZ Design of analog CMOS integrated circuits | 621.39732 RAZ Design of analog CMOS integrated circuits |
The large scale integration and planar scaling of individual system chips is reaching an expensive limit. If individual chips now, and later terrabyte memory blocks, memory macros, and processing cores, can be tightly linked in optimally designed and processed small footprint vertical stacks, then performance can be increased, power reduced and cost contained. This book reviews for the electronics industry engineer, professional and student the critical areas of development for 3D vertical memory chips including: gate-all-around and junction-less nanowire memories, stacked thin film and dou.
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