Design and optimization of high voltage (HV) drain extended FinFET transistors for analog SoC applications
Pal, Priyanjana
Design and optimization of high voltage (HV) drain extended FinFET transistors for analog SoC applications - Gandhinagar : Indian Institute of Technology Gandhinagar, 2020 - ix, 60p. : ill. ; 30 cm.
Including bibliography details
18250024
M.Tech
Electrical Engineering
Sub-micron CMOS Technology
Drain-extended FinFET (DeFinFET)
High Voltage Devices
Planar MOSFETs
621.3 / PAL
Design and optimization of high voltage (HV) drain extended FinFET transistors for analog SoC applications - Gandhinagar : Indian Institute of Technology Gandhinagar, 2020 - ix, 60p. : ill. ; 30 cm.
Including bibliography details
18250024
M.Tech
Electrical Engineering
Sub-micron CMOS Technology
Drain-extended FinFET (DeFinFET)
High Voltage Devices
Planar MOSFETs
621.3 / PAL
