Kumar, Pawan <br/><br/>
Digital compute in memory chip design and validation 

 - Gandhinagar:   Indian Institute of Technology Gandhinagar,  2025 
 - x, 59p.:   hbk.:  30 cm 
<br/><br/>Includes References 
<br/><br/><label>Subjects--Topical Terms: </label><br/>23250028<br/>M. Tech<br/>Electrical Engineering<br/>Integrated Circuits<br/>Artificial Inteligence<br/>Internet of Things<br/>Graphic Data System<br/>Application-Specific Integrated Circuits (ASICs)<br/>CMOS Technology
<br/><br/><label>Dewey Class. No.: </label>621.3 KUM