Pal, Priyanjana <br/><br/>
Design and optimization of high voltage (HV) drain extended FinFET transistors for analog SoC applications 

 - Gandhinagar :  Indian Institute of Technology Gandhinagar,   2020 
 - ix, 60p. :  ill. ;  30 cm. 
<br/><br/>Including bibliography details 
<br/><br/><label>Subjects--Topical Terms: </label><br/>18250024<br/>M.Tech<br/>Electrical Engineering <br/>Sub-micron CMOS Technology<br/>Drain-extended FinFET (DeFinFET)<br/>High Voltage Devices<br/>Planar MOSFETs
<br/><br/><label>Dewey Class. No.: </label>621.3  / PAL