TY  - GEN
AU  - Prince, Betty
TI  - Vertical 3D memory technologies
SN  - 9781118760512
U1  - 621.39732 PRI 
PY  - 2014///
CY  - Chichester
PB  - John Wiley &​ Sons Ltd.
KW  - Strains and Stresses -- Simulation Methods.
KW  - TECHNOLOGY &​ ENGINEERING -- Mechanical.
KW  - Three-Dimensional Integrated Circuits.
KW  - Semiconductor Storage Devices.
KW  - Three-Dimensional Integrated Circuits -- Design.
N2  - The large scale integration and planar scaling of individual system chips is reaching an expensive limit. If individual chips now, and later terrabyte memory blocks, memory macros, and processing cores, can be tightly linked in optimally designed and processed small footprint vertical stacks, then performance can be increased, power reduced and cost contained. This book reviews for the electronics industry engineer, professional and student the critical areas of development for 3D vertical memory chips including: gate-all-around and junction-less nanowire memories, stacked thin film and dou.


ER  -