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Indigenous technology development of high-voltage MOS transistors for power management applications

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Material type: Book

BookPublication details: Gandhinagar: Indian Institute of Technology Gandhinagar, 2023.Description: xxxv, 172p.: ill.; hbk; 30 cmSubject(s):

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Holdings
Item type	Current library	Collection	Call number	Status	Date due	Barcode
Theses (Ph.D)	IIT Gandhinagar	Reference	621.381528 KAU (Browse shelf(Opens below))	Available		T01079

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Previous	621.3815 UYE Chip design for submicron VLSI: CMOS layout and simulation	621.3815 UYE Chip design for submicron VLSI: CMOS layout and simulation	621.3815 YEL Evaluating the scaling effects on synchronizers and global interconnects on multicore SoCs	621.381528 KAU Indigenous technology development of high-voltage MOS transistors for power management applications	621.3815284 JAI Effect of device geometries on HCI and PBTI of gate first High-K metal gate NMOS transistors	621.3815284 PAR Analysis and modeling of stress over layer induced threshold voltage shift in High-K metal gate MOSFETs	621.38153 HWA Digital Logic and Microprocessor Design with VHDL	Next

Includes bibliography.

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