Chip design for submicron VLSI: CMOS layout and simulation

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Material type: Book

BookPublication details: New Delhi: Cengage Learning, 2006.Edition: India EditionDescription: xvi, 411 p: ill; 25cmISBN:

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Holdings
Item type	Current library	Collection	Call number	Status	Barcode
Books	IIT Gandhinagar	General	621.3815 UYE (Browse shelf(Opens below))	Available	002269
CD/DVD	IIT Gandhinagar	Reference	621.3815 UYE (Browse shelf(Opens below))	Available	C00130
Books	IIT Gandhinagar	General	621.3815 UYE (Browse shelf(Opens below))	Available	008181
CD/DVD	IIT Gandhinagar	Reference	621.3815 UYE (Browse shelf(Opens below))	Available	C00478

Previous	No cover image available				No cover image available	No cover image available	No cover image available	Next
Previous	621.3815 NAV Embedded core design with FPGAs	621.3815 NIL Introductory circuits for electrical and computer engineering	621.3815 UYE Chip design for submicron VLSI: CMOS layout and simulation	621.3815 UYE Chip design for submicron VLSI: CMOS layout and simulation	621.3815 YEL Evaluating the scaling effects on synchronizers and global interconnects on multicore SoCs	621.381528 KAU Indigenous technology development of high-voltage MOS transistors for power management applications	621.3815284 JAI Effect of device geometries on HCI and PBTI of gate first High-K metal gate NMOS transistors	Next

Includes bibliographical references and index.

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