Sip system-in-package design and simulation: mentor EE flow advanced design guide (Record no. 64102)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 01762nam a22002297a 4500 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9781119046011 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.38152 SUN |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Suny Li (Li Yang) |
| 245 ## - TITLE STATEMENT | |
| Title | Sip system-in-package design and simulation: mentor EE flow advanced design guide |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Name of publisher, distributor, etc. | Wiley, |
| Date of publication, distribution, etc. | 2024. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE | |
| Bibliography, etc. note | Include Index |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. | An advanced reference documenting, in detail, every step of a real System-in-Package (SiP) design flow<br/><br/>Written by an engineer at the leading edge of SiP design and implementation, this book demonstrates how to design SiPs using Mentor EE Flow. Key topics covered include wire bonding, die stacks, cavity, flip chip and RDL (redistribution layer), Embedded Passive, RF design, concurrent design, Xtreme design, 3D real-time DRC (design rule checking), and SiP manufacture. <br/><br/>Extensively illustrated throughout, System in Package Design and Simulation covers an array of issues of vital concern for SiP design and fabrication electronics engineers, as well as SiP users, including: <br/><br/>Cavity and sacked dies design<br/>FlipChip and RDL design<br/>Routing and coppering<br/>3D Real-Time DRC check<br/>SiP simulation technology<br/>Mentor SiP Design and Simulation Platform<br/>Designed to function equally well as a reference, tutorial, and self-study, System in Package Design and Simulation is an indispensable working resource for every SiP designer, especially those who use Mentor design tools. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Components |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Circuits |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Devices and Systems |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | General Topics for Engineers |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Dielectrics and Plasmas |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Engineered Materials |
| 856 ## - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | <a href="https://ieeexplore.ieee.org/book/10518287">https://ieeexplore.ieee.org/book/10518287</a> |
| Link text | Click here to access e-book |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | Dewey Decimal Classification |
| Koha item type | E- Books |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Materials specified (bound volume or other part) | Damaged status | Not for loan | Home library | Current library | Date acquired | Total Checkouts | Full call number | Date last seen | Uniform Resource Identifier | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Dewey Decimal Classification | IEEE-Wiley Semiconductor Ebooks | IIT Gandhinagar | IIT Gandhinagar | 10/11/2025 | 621.38152 SUN | 10/11/2025 | https://ieeexplore.ieee.org/book/10518287 | 10/11/2025 | E- Books |
