Digital VLSI design and simulation with verilog (Record no. 62998)
[ view plain ]
| 000 -LEADER | |
|---|---|
| fixed length control field | 02687nam a2200253 4500 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9781119778066 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.38152 TRI |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Tripathi, Suman Lata |
| 245 ## - TITLE STATEMENT | |
| Title | Digital VLSI design and simulation with verilog |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Name of publisher, distributor, etc. | Wiley, |
| Date of publication, distribution, etc. | 2024 |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. | Master digital design with VLSI and Verilog using this up-to-date and comprehensive resource from leaders in the field<br/><br/>Digital VLSI Design Problems and Solution with Verilog delivers an expertly crafted treatment of the fundamental concepts of digital design and digital design verification with Verilog HDL. The book includes the foundational knowledge that is crucial for beginners to grasp, along with more advanced coverage suitable for research students working in the area of VLSI design. Including digital design information from the switch level to FPGA-based implementation using hardware description language (HDL), the distinguished authors have created a one-stop resource for anyone in the field of VLSI design.<br/><br/>Through eleven insightful chapters, you�ll learn the concepts behind digital circuit design, including combinational and sequential circuit design fundamentals based on Boolean algebra. You�ll also discover comprehensive treatments of topics like logic functionality of complex digital circuits with Verilog, using software simulators like ISim of Xilinx. The distinguished authors have included additional topics as well, like:<br/><br/>A discussion of programming techniques in Verilog, including gate level modeling, model instantiation, dataflow modeling, and behavioral modeling<br/>A treatment of programmable and reconfigurable devices, including logic synthesis, introduction of PLDs, and the basics of FPGA architecture<br/>An introduction to System Verilog, including its distinct features and a comparison of Verilog with System Verilog<br/>A project based on Verilog HDLs, with real-time examples implemented using Verilog code on an FPGA board<br/>Perfect for undergraduate and graduate students in electronics engineering and computer science engineering, Digital VLSI Design Problems and Solution with Verilogalso has a place on the bookshelves of academic researchers and private industry professionals in these fields. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Circuits |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Devices |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Engineered Materials |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Dielectrics |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Plasmas |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | IEEE-Wiley Semiconductor Ebooks |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Saxena, Sobhit |
| Relator term | Co author |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Sinha, Sanjeet K. |
| Relator term | Co author |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Patel, Govind S. |
| Relator term | Co author |
| 856 ## - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | <a href="https://ieeexplore.ieee.org/servlet/opac?bknumber=10513526">https://ieeexplore.ieee.org/servlet/opac?bknumber=10513526</a> |
| Link text | Click here to access e-book |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | Dewey Decimal Classification |
| Koha item type | E- Books |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Materials specified (bound volume or other part) | Damaged status | Not for loan | Home library | Current library | Date acquired | Total Checkouts | Full call number | Date last seen | Uniform Resource Identifier | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Dewey Decimal Classification | IEEE-Wiley Semiconductor Ebooks | IIT Gandhinagar | IIT Gandhinagar | 17/06/2025 | 621.38152 TRI | 17/06/2025 | https://ieeexplore.ieee.org/servlet/opac?bknumber=10513526 | 17/06/2025 | E- Books |
